System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications
PDF
  • eBook:
    System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications
  • Author:
    Ashok B. Mehta
  • Edition:
    3rd ed. 2020 edition
  • Categories:
  • Data:
    2019-10-10
  • ISBN:
    3030247368
  • Language:
    English
  • Pages:
    507
  • Format:
    PDF

Book Description

System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications by Ashok B. Mehta

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures.
·         Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;
·         Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies;
·         Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;
·         Explains each concept in a step-by-step fashion and applies it to a practical real life example;
·         Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.

Content

1. Introduction

Part I System Verilog Assertions (SVA)
2. System Verilog Assertions
3. Sequential Domain Coverage (“Cover” Property and “Cover” Sequence)
4. Conventions Used in the Book
5. Immediate Assertions
6. Concurrent Assertions: Basics
7. Sampled Value Functions
8. Operators
9. System Functions and Tasks
10. Multiple Clocks
11. Local Variables
12. Recursive Property
13. Endpoint of a Sequence (.triggered and .matched)
14. “expect”
15. “assume” and “restrict” for Simulation and Formal (Static Functional) Verification
16. Clock Domain Crossing (CDC) Verification Using Assertions
17. Important Topics
18. Asynchronous FIFO Assertions
19. Asynchronous Assertions
20. IEEE-1800-2009/2012 Features
21. “let” Declarations
22. Checkers
23. SystemVerilog Assertions LABs
24. System Verilog Assertions: LAB Answers

Part II System Verilog Functional Coverage (FC)
25. Functional Coverage
26. Functional Coverage: Language Features
27. Performance Implications of Coverage Methodology
28. Coverage Options

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